The invention is in the field of metal-oxide-semiconductor (MOS) field-effect devices, and relates specifically to lateral insulated gate transistors.
MOS devices are generally well-known in the art, and a typical prior art high-voltage lateral DMOS transistor is shown in FIG. 1 of U.S. Pat. No. 4,300,150. This device includes a semiconductor substrate of a first conductivity type (p-type), an epitaxial surface layer of a second conductivity type (n-type) on a major surface of the substrate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer, a surface-adjoining source region of the second conductivity type in the channel region, and a surface-adjoining drain region of the second conductivity type in the epitaxial layer and spaced apart from the channel region. An insulating layer is provided on the epitaxial surface layer and covers at least that portion of the channel region located between the source and drain. A gate electrode is provided on the insulating layer, over the portion of the channel region located between the source and drain and is electrically isolated from the epitaxial surface layer by the insulating layer (referred to as the gate oxide), while source and drain electrodes are connected respectively to the source and drain regions of the transistor. Such prior art high-voltage DMOS transistors typically have a relatively thick epitaxial layer, in the order of about 25-30 micrometers for a breakdown voltage of about 250 V.
It has been found that the breakdown characteristics of high-voltage semiconductor devices can be improved by using the REduced SURface Field (or RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electronic Devices Meeting Technical Digest", Dec., 1979, pages 238-240, by Appels et al, and U.S. Pat. No. 4,292,642, incorporated hereby by reference. Essentially, the improved breakdown characteristics of RESURF devices are achieved by employing thinner but more highly doped epitaxial layers to reduce surface fields. Additionally, surface and buried regions having no direct external connections have been used to redistribute surface fields in MOS devices, as shown, for example, in U.S. Pat. No. 4,300,150 and Japanese Kokai No. 45074-81. The use of Schottky contacts in field effect transistors is described in the article entitled "Analysis and Characterization of the Hybrid Schottky Injection Field Effect Transistor", International Electronic Devices Meeting, 1986, IDEM86, pages 222-224, by J. K. O. Sin, et al.
The RESURF technique was applied to lateral double-diffused MOS transistors, as reported in "Lateral DMOS Power Transistor Design", "IEEE Electron Device Letters", Vol. EDL-1, pages 51-53, Apr., 1980, by Colak et al, and the result was a substantial improvement in device characteristics. In high-voltage DMOS devices, there is normally a trade-off between breakdown voltage and "on" resistance, with the goal being to increase the breakdown voltage level while maintaining a relatively low "on" resistance. Using the RESURF technique, and for reference assuming a constant breakdown voltage, an improvement (e.g. decrease) in "on" resistance by a factor of about 3 may be obtained in a device occupying the same area as a conventional (thick epitaxial layer) DMOS device. Nevertheless, a further improvement in the "on" resistance characteristics of such devices would be extremely desirable, particularly for high-voltage power devices where "on" resistance is an important parameter. Ideally, such an improvement should be obtained without significantly degrading breakdown voltage or switching characteristics.
In seeking to create more efficient power switching devices, a new type of device, the Lateral Insulated Gate Transistor (hereinafter LIGT) was recently developed. Various LIGT structures are shown in European Patent Application No. 0 111 803. The LIGT essentially modifies the LDMOS structure of the general type described above with an anode region implanted near the drain region. In the LIGT, during the "on" state, current is conducted by the electron-hole plasma. The electrons are injected from the accumulation region under the gate and the holes are injected from the anode, resulting in conductivity modulation of the drift region. The current is dominated by the recombination mechanism in a manner similar to a p-i-n diode. As current increases, size of the holes injected by the anode flow through the substrate, forward biasing the epi-substrate junction. The substrate becomes partially conductivity-modulated and also contributes to the recombination current. At a high current level, holes injected from the anode may flow through the channel resistance, forward biasing the double-diffused junction, and thus resulting in latch-up.
In the LIGT, the addition to the anode region changes the mechanism of the current conduction in the device's drift region. In the "on" state, the current is initially conducted by the majority carriers, as in LDMOS transistors Electrons flow from the source through the gated inversion region, through the drift region (which is the largest contributor towards the "on" resistance), and then into the drain. When drain current reaches a level high enough to forward bias the drain junction, the drain starts injecting holes into the drift region, forming a neutral plasma. The density of these injected minority carriers is higher than the doping level of the impurities in the drift region. The injected carriers modulate the resistance of the drift region, thus reducing overall "on" resistance. The injected minority carriers can flow both into the substrate and onto the channel region.
Although the LIGT offers several important advantages, including high current handling capabilities, low "on" resistance and high breakdown voltage, these devices have heretofore suffered from a significant drawback. In the LIGT, the turn-off process is determined by recombination of minority carriers, and since no contact is provided for the removal of electrons, the turn-off time is relatively long. Typically, turn-off times are in the range of 3-10 microseconds, while turn-on times are much less than 1 microsecond. This drawback is described in "Comparison of High Voltage Devices for Power Integrated Circuits", by Jayaraman, Rumennik et al, International Electron Devices Meeting, pp. 258-261, Dec., 1984.